Examining the Consequences of High-Level Synthesis Optimizations on Power Side-Channel

High-level synthesis (HLS) allows hardware designers to think algorithmically and not worry about low-level, cycleby-cycle details. This provides the ability to quickly explore the architectural design space and tradeoff between resource utilization and performance. Unfortunately, security evaluation is not a standard part of the HLS design flow. In this work, we aim to understand the effects of HLS optimizations on power sidechannel leakage. We use Xilinx Vivado HLS to develop different AES cores, implement them on a Spartan 6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and information leakage through power consumption. Furthermore, we analyze the information leakage of some common hand-written register transfer level (RTL) crypto cores. We describe an evaluation procedure for power side-channel leakage and use it to make recommendations about how to design more secure architectures.